Design of ultra-low voltage CCII utilizing level shifting technique and a dual mode multifunction universal filter as an application
Abstract
The paper presents an implementation of ultra low voltage second generation current conveyor (ULV-CCII). The methodology adopted for the design is the use of level shifting stage to lower the effective threshold voltage of the PMOS differential pair transistors. The combination of conventional and level shifted P-MOS differential pairs together with low voltage folded cascode output sage was used to achieve almost rail to rail operation at an ultra low supply of ±0.4V. This approach also benefits from increased common mode range. The CCII provides voltage transfer bandwidth of 7.8 MHz and the current transfer bandwidth of 17 MHz while dissipation a nominal power of 123 μW. A versatile dual mode universal filter is realized to validate the functionality of the ULV-CCII. The filter is capable of working in both current and voltage mode without change in its topology. The filter employs only two CCIIs, two capacitors and two resistors. The use of only positive single input CCII simplifies the implementation and relaxes the matching constraints during layout leading to enhanced filter performance. The filter works at ±0.4V supply and provides all standard filter responses in voltage mode as well as low pass and band pass response for current mode of operation. The H-spice simulation results in 0.18μm TSMC CMOS technology are presented to prove the results.
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