Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Applications

Abstract

There is an immense necessity of several kb of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45v.