Implementation of Edge Detection Algorithm using FPGA Reconfigurable Hardware
Abstract
Digital image processing is known as computer manipulation of image, which includes algorithms like image enhancement and target reorganization. Some of these algorithms involve operations like convolution and edge detection, which requires high computation. Generally, the software running on processor performs these manipulations. To achieve higher computation performance in terms of execution time, these algorithms are implemented on reconfigurable hardware like FPGA. One can implement parallel architecture and pipelined architecture on FPGA to gain speed up. In this work, we provide a detailed description of implementing edge detection algorithm on SGI–RC100 platform. The algorithm is implemented using ANSI-C to manipulate the host program and Mitrion–C language. Mitrion–C offers efficient way to write code for parallel and pipelined architecture to preform edge detection. Then, the algorithm is tested on Intel Intanium 2 based architecture and compared its execution time with RC 100 platform based algorithm to check the speed up gain by FPGA based algorithm. The experimental results showed that the speed of the reconfigurable hardware FPGA based algorithm outperformed the software-based approach by more than 50 times.
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