Design of an Efficient Reverse Converter for Moduli Sets

Abstract

In this paper, the reverse converter design for moduli sets  is proposed. This design for five moduli sets by using the new Chinese Remainder Theorem (CRT-1) formulates the wide modular devaluation. The appropriate selection of moduli has a significant impact on the reverse converter's speed and complexity. The modified converter depends upon the arithmetic designs that are implemented without the read - only memories and lookup tables. The Carry Save Adder and Carry Propagate Adder are used in the reverse converter and modulo adder gives higher speed and less hardware complexity. The proposed converter has been implemented to get the conversion time and area as supported by the reverse converter of 12-bits and maximum up to 100-bits.