Optimizing CNTFET design parameters using Taguchi method for high performance and low power applications

Abstract

CNTFET technology has an excellent electrical characteristic hence become an effective way to achieve high performance and low power consumption devices.  In this work, the Taguchi method was implemented to determine the best combination of factors for robust device performance using orthogonal arrays, signal-to-ratio as well as Pareto analysis of variance as the quality characteristic of choices.  The factors involved in the design of experiments include the diameter of CNT, the pitch between CNT, and the number of CNT in the transistors.  It is observed that with a CNT diameter of 1.4 nm, 5 nm pitch, and 5 CNT, the best performance in terms of on-current can be achieved with the value of 110Ua. CNT diameter of 1.0 nm, 3 nm pitch, and 1 CNT led to a better performance in terms of off-current with the value of 0.000178uA.  As for the current ratio, the value best is achieved at the ratio of 87982.029 with 1.0 nm of CNT diameter, 5 nm of CNT pitch, and 3 tubes in the CNTFET.  Further examination on inverter circuits shows that the optimization led to the delay and average power reduction by 13% and 15% respectively.